This application is based upon and claims priority from prior Italian Patent Application No. MI99A002651, filed Dec. 20, 1999, the entire disclosure of which is herein incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a non-volatile high-performance memory device, more specifically a MOS or CMOS memory device and a process for the manufacture of a MOS or CMOS memory device.
2. Description of Related Art
Non-volatile memories are used widely in systems containing microprocessors or in other types of integrated circuits. Because of today""s need of non-volatile memories with higher and higher performance memory capacity, semiconductor manufacturers are carrying out continuous research into the reduction of the dimensions of the memories and an increase in the density of the data stored.
For reasons which concern the consumption of power, the single nonvolatile memory cell usually consists of a MOS N-channel or P-channel transistor while the reading circuitry of the memory cells is usually made by CMOS technology. Therefore an array of memory cells coincides with an array of transistors whose reading current (with special polarization of the drain and gate terminals of the memory cell that has been addressed) determines the logic state of the cell, that is, if the cell is ON (logic state 1 or ON state) or is OFF (logic state 0 or OFF state).
The differentiation of the ON or OFF cells can come about physically by interrupting the current path between drain and source, for example, by eliminating the contact of one of the terminals or interrupting the active area.
It is also possible to carry out the programming of the non-volatile memories by implanting or not implanting the source and drain junctions when the corresponding plants are carried out in the transistors. In this case memories which are difficult to decode are obtained, that is they are relatively safe, as required by various SMART CARD applications.
A process for producing a memory whose programming is carried out by means of the above-mentioned technique is described in EP 0575688, which is herein incorporated by reference in its entirety. The EP 0575688 patent describes a process for manufacturing and programming a non-volatile ROM memory consisting of a matrix of memory cells arranged in lines and columns and each of the cells has drain and source regions of the LDD type (lightly diffused drain) separated by a channel region overlapped by the gate structure in a semiconductor substrate. The process includes the steps of formation of the structure of the gate, of the drain regions and the formation of a dielectric spacer at the sides of the gate. The process is characterized by a succession of steps which provide the definition of a portion of the drain area that is adjacent to the gate of the memory cell that is programmed in OFF state, making it permanently non-conductive by subsequently implanting a dopant with conductivity of the same type as that of the substrate. Following this implanting, a new mask is used for a successive implant step of the source region of the cell to increase the doping level. Next a layer of dielectric is formed. The openings to contact the drain regions of the memory cells are defined. A dopant is implanted to increase the doping level of the regions below the contact areas and the drain contacts are formed.
The process described above although useful, is not without its shortcomings. One shortcoming is the need to provide higher performance or faster memory cells. In order to provide faster memory cells, designers of memory cells form silicide on the gates and silicide on the junctions. However, silicide cannot be formed on layers of silicon that are only slightly doped because the known processes for the formation of the silicide consumes both metal and silicon. For example a junction with silicide, such as an LDD junction with silicide, would result in a short circuit in the substrate due to the dispersion of the metal in the silicide layer.
Accordingly, a need exists to provide a process and a non-volatile memory cell to overcome this shortcoming.
Briefly, in accordance with the present invention, a non-volatile memory device consisting of memory cells, each one formed as a MOS transistor with source and drain regions and a gate structure with a dielectric spacer placed at the sides of the gate, some of the memory cells being in an ON state and other memory cells in an OFF state, the memory cells in the ON state having drain and source regions of the LDD type, characterized in that the drain and source regions of the memory cells in the OFF state are formed by highly doped regions and the memory cells in the ON state and the memory cells in the OFF state show layers of silicide above their active regions.
In another embodiment, a manufacturing process is disclosed for making a high performance non-volatile memory device using silicide.